Semiconductor device and method of manufacturing the same

ABSTRACT

A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film  14 , a first conductive layer  15  and a first insulating film  16  on a semiconductor layer  13  provided on an insulating film  12 ; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film  17  in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and amethod of manufacturing the same, and more particularly, relates to astructure of a semiconductor device using an SOI (Silicon On Insulator)substrate that has a single crystal semiconductor layer formed through aburied oxide film on a semiconductor substrate, and an elementseparating method.

BACKGROUND ART

[0002] The request of a miniaturization and high density fabrication ofLSI has become much severer, and a sub 100-nm generation has come. Onthe other hand, the request of a low power consumption and high speedoperation has been increased. It becomes difficult to satisfy thoserequests by using a conventional bulk substrate.

[0003] MISFET (Metal-Insulator-Semiconductor Field Effect Transistor)formed on an SOI substrate is expected as a ULSI element in the sub100-nm generation, since junction capacitances in source and drainregions are small, a substrate bias effect is low and a sub-thresholdcharacteristic is excellent, as compared with conventional MISFET formedon a bulk substrate.

[0004] The SOI-MISFET is grouped into two kinds of operation modes of afully-depleted SOI-MISFET (hereafter, referred to as an FD-typeSOI-MISFET) and a partially-depleted SOI-MISFET (hereafter, referred toas PD-SOI-MISFET). In the FD-type SOI-MISFET, the film thickness of aSOI layer is thinner than a maximum depletion layer (a body region isalways in a depleted state), whereas in the PD-type SOI-MISFET, the filmthickness of the SOI layer is thicker than a maximum depletion layer. Inparticular, the FD-type SOI-MISFET could be expected as the ULSI elementhaving a low voltage operation and an excellent ultra high speedoperation since a sharp sub-threshold characteristic can be obtained. Inthe FD-type SOI-MISFET in the sub 100 nm generation, the film thicknessof a silicon layer on an SOI substrate is reduced to about 10 nm orless.

[0005] A method of manufacturing a conventional SOI-MISFET will bedescribed below.

[0006] At first, a case that a shallow trench isolation (hereafter,referred to as STI) is applied to a typical MISFET on a bulk substratewill be described with reference to sectional views of FIGS. 1A to 2B(hereafter, referred to as a first conventional example). An SOIsubstrate is provided which has a silicon substrate 51, a buried oxidefilm 52 and a silicon film 53 (FIG. 1A). A pad oxide film 54 having thefilm thickness of about 5 nm and a stopper nitride film 55 of about 120nm are sequentially deposited. Then, by using a photo-lithography and areactive ion etching (hereafter, referred to as RIE) method, the stoppernitride film 55, the pad oxide film 54 and the silicon film 53 arepatterned to an island shape, and element isolation trenches are formed(FIG. 1B). Subsequently, an STI embedded insulating film 57 isdeposited, and a chemical mechanical polishing (hereafter, referred toas CMP) method is used to flatten the STI embedded insulating film 57(FIG. 1C).

[0007] Next, the stopper nitride film 55 is removed by wet etching ofhot phosphoric acid, and the pad oxide film 54 is removed by wet etchingof fluoric acid, such that the silicon film 53 is exposed (FIG. 1D). Atthis time, the buried oxide film 52 in the lower portion of the siliconfilm 53 is over-etched 59. Then, a gate insulating film 60 is formed,and a polysilicon film 61 is deposited, and then is patterned to form agate electrode (FIG. 2A). Subsequently, side wall insulating films 63,source and drain regions 64 and a silicide film 65 are formed, and aninterlayer insulating film 66 is deposited. Then, contact holes areopened, and metal wirings 67 are formed. Thus, the MISFET is formed(FIG. 2B). FIG. 2C is a plan view showing the MISFET. FIGS. 1A to 2B aresectional views of the MISFET along a line A-A′ of FIG. 2C.

[0008]FIGS. 3A to 3D are sectional views showing a method of forming anelement insulation region disclosed in Japanese Laid Open PatentApplication (JP-A 2001-24202) (hereafter, referred to as a secondconventional example). A gate insulating film 68 and a first polysiliconfilm 70 are deposited in this order on the surface of the silicon filmof the SOI substrate in which the buried oxide film 52 and the siliconfilm 53 are laminated on a silicon substrate 51. Then, the firstpolysilicon film 70, the gate insulating film 68 and the silicon film 53are patterned by using a same mask (FIG. 3A). Subsequently, an STIembedded insulating film 69 is deposited on the entire surface, and isflattened by using a CMP method (FIG. 3B).

[0009] Next, a second polysilicon film 71 is deposited on the entiresurface, and a mask pattern 58 of photo resist is formed (FIG. 3C). Byusing this mask pattern 58, the second polysilicon film 71, the firstpolysilicon film 40 and the gate insulating film 68 are patterned by aRIE method. Here, the first polysilicon film 70 functions as a gateelectrode 70 a, and the second polysilicon film 71 functions as a gateelectrode wiring line 71 a through which gate electrodes of transistorsadjacent to each other are connected. Subsequently, source and drainregions 64 are formed by ion implantation. Thus, the structure of FIG.3D is obtained.

[0010] In the SOI-MISFET, it is known that the exposure of ends 72 of anelement region causes a leak current to flow. However, according to thiselement insulation method, the side of the silicon film 53 on which theelement is formed is covered with the STI embedded insulating film 69.Thus, the ends 72 of the element region are not exposed, and the leakcurrent is suppressed (it should be noted that the location where theleak current is generated is the end existing in a directionperpendicular to FIG. 3D, but it is shown in FIG. 3D for theillustrative convenience).

[0011] A typical film thickness of a silicon film is about 10 nm in ahigher density generation. However, if the STI structure is applied tothe SOI-MISFET having such a thin silicon film, there are the followingproblems in the first conventional example. After the formation of theshape shown in FIG. 1C, the stopper nitride film 55 is removed by thewet etching method of the hot phosphoric acid, and the pad oxide film 54is further removed by the wet etching method of HF. At this time, theSTI embedded insulating film 57 is also etched by HF at the same time.Thus, as shown in FIG. 1D, the buried oxide film 52 under the siliconfilm 53 is over-etched (numeral 59 of FIG. 1D). In particular, if thesilicon film 53 is thin (for example, in a case of 10 nm), when the padoxide film 54 is etched, the entire STI embedded insulating film 57 onthe side of the silicon film 53 is easily lost through the etching.Therefore, the over-etching 59 is extremely easily caused in the lowercorner of the end of the silicon film 53.

[0012] Moreover, the gate insulating film 60 is formed in the state thatthe buried oxide film 52 at the lower corner of the end of the siliconfilm 53 is over-etched. Then, the polysilicon film 61 is deposited.Subsequently, when the polysilicon film 61 is patterned, a residualpolysilicon film 62 is left in the over-etched portion 59 (FIG. 2A).

[0013] As shown in the plan view of FIG. 2C, the residual polysiliconfilm 62 is formed to surround an active region (an island region). Thisresults in the connection between the residual polysilicon film 62 andthe polysilicon film 61 on a B-B′ section. At this time, if two or moregate electrodes are arranged in parallel to each other, the gateelectrodes are short-circuited to each other through the residualpolysilicon film 62. In addition, a capacitance generated between theresidual polysilicon film 62 and each of the source and drain regions 64functions as a parasitic capacitance connected in parallel to the gatecapacitance. This increases a load on the circuit to decrease theoperation speed. Also, if the insulation characteristic of the gateinsulating film 60 is deteriorated due to the damage caused by the ionimplantation to form the source and drain regions 64, there may be apossibility that an electric short-circuit is caused between the gateelectrode and the each of the source and drain regions 64 through theresidual polysilicon film 62.

[0014] Also, if the formation of the over-etched portion 59 causes theelement end to be exposed, a leak current easily flows in the end(numeral 72 of FIG. 3D) of the element region.

[0015] Moreover, in the first conventional example, the end of theelement region is exposed so that the gate electrode is formed to coverthe side of the element region. Therefore, the electric field applied tothe silicon film from the gate electrode is increased. Thus, the reversenarrow channel effect becomes severe to decrease the threshold throughthe miniaturization.

[0016] In order to prevent the above-mentioned over-etching, it could beconsidered to strictly control the wet etching of the pad oxide film 54by HF, although this control is very difficult actually. At this time, astep will be generated as shown in FIG. 4. This is because the filmthickness of the pad oxide film 54 is very thinner than that of the STIembedded insulating film 57. Also, if the wet etching with HF iscontinued in order to remove this step, the above-mentioned over-etchedportion would be generated.

[0017] Here, the problem when the step is generated will be describedwith reference to FIG. 5. In case of the existence of such a step, whenthe polysilicon film 61 is deposited (FIG. 5A) after the formation ofthe gate insulating film 60, and the gate electrode is formed by etchingthis polysilicon film 61 by the RIE method, non-etched polysilicon films62 is remained in the step portions (FIG. 5B). This residual polysiliconfilm 62 acts as a cause of short circuit between the polysilicon filmsor between the gate electrode and each of the source and drain regions.Also, such a step deteriorates the shape of a resist pattern for a gateelectrode in a lithography step.

[0018] Also, in the second conventional example, if a polishingoperation is carried out by the CMP method in order to process as shownin FIG. 3B, the first polysilicon film 70 is polished deeper than theSTI embedded insulating film 69, because a polishing rate of thepolysilicon film is typically larger than a polishing rate of the oxidefilm. This results in the formation of a step (FIG. 6A). Moreover, thefirst polysilicon film 70 can not function as a stopper to the polishingoperation in the CMP method. Therefore, if the polysilicon film is athin film, there may be a possibility that the polysilicon film isperfectly lost (FIG. 6B).

[0019] By the way, a semiconductor device is disclosed in Japanese LaidOpen Patent Application (JP-A-Heisei 11-74538). The semiconductor deviceof this conventional example has a substrate having an insulating layer.A first conductive type semiconductor layer is formed on the insulatinglayer such that a part of the semiconductor layer functions as a channelregion. A gate insulating film is formed on the channel region of thesemiconductor layer, and a gate electrode is formed on the gateinsulating layer. A second conductive type source and drain regions arerespectively formed on both sides of the channel region within thesemiconductor layer. A hole removing region is formed in a region withinthe semiconductor layer, and the hole removing region is adjacent to thechannel region and at least one region of the source region and thedrain region, and has a function of preventing the accumulation of ahole of a pair of a hole and an electron generated in the channelregion.

[0020] Also, a SOI device is disclosed in Japanese Laid Open PatentApplication (JP-A 2001-24202). The SOI device of this conventionalexample contains an SOI substrate constituted of a lamination structureof a base substrate, a buried oxide film and a semiconductor layer. Anoxide film is formed so as to be in contact with the buried oxide filmin a semiconductor portion of a field region so as to determine anactive region. Each of gate electrode patterns has a gate oxide filmformed only on the active region, and source and drain regions areformed within the active regions of the semiconductor layer on bothsides of the gate electrode pattern. A gate electrode line is formed onthe gate electrode pattern and the field region to connect the gateelectrode patterns formed on the respective aligned active regions.

[0021] Also, a separation structure of a semiconductor device isdisclosed in Japanese Laid Open Patent Application (JP-A-Heisei,11-67895). The separation structure of the semiconductor device includesa semiconductor substrate having an active region and a field region. Aburied insulating layer is formed in a predetermined depth within theactive region of the semiconductor substrate, and a separation layer isformed in a position deeper than the buried insulating layer within thefield region of the semiconductor substrate.

DISCLOSURE OF INVENTION

[0022] Therefore, a subject of the present invention is to solve theabove-mentioned problems. Therefore, an object of the present inventionis firstly not to expose an element region end, secondly not to generatea residual polysilicon, and thirdly not to damage or lose a polysiliconfilm as a gate electrode.

[0023] A method of manufacturing a semiconductor device in the presentinvention includes the steps of: (a) sequentially forming a gateinsulating film, a first conductive layer and a first insulating film ona semiconductor layer of an insulating film; (b) selectively removingthe semiconductor layer, the gate insulating film, the first conductivelayer and the first insulating film and forming a device isolationtrench; (c) forming a second insulating film on the device isolationtrench wherein a height of an upper surface of the second insulatingfilm substantially coincides with a height of an upper surface of thefirst insulating film; (d) removing a part of the second insulating filmand the first insulating film and making a height of an upper surface ofthe exposed first conductive layer substantially coincide with theheight of the top surface of the second insulating film; and (e)patterning the first conductive layer and forming a gate electrode.

[0024] In a method of manufacturing a semiconductor device in thepresent invention, the step (d) is done by using RIE (Reactive IonEtching).

[0025] In the method of manufacturing the semiconductor device in thepresent invention, at the step (d), the removal of the part of thesecond insulating film is done by the RIE, and the removal of the firstinsulating film is done by wet etching.

[0026] In a method of manufacturing a semiconductor device in thepresent invention, it further includes the step of (f) forming a secondconductive layer on the first conductive layer after the step (d), andat the step (e), the first conductive layer and the second conductivelayer are patterned to thereby form a gate electrode and a gate pullingwiring pulled out from the gate electrode.

[0027] A method of manufacturing a semiconductor device in the presentinvention includes the steps of: (g) sequentially forming a gateinsulating film, a first conductive layer and a first insulating film ona semiconductor layer of an insulating film; (h) selectively removingthe semiconductor layer, the gate insulating film, the first conductivelayer and the first insulating film and forming a device isolationtrench; (i) forming a second insulating film on the device isolationtrench wherein a height of an upper surface of the second insulatingfilm substantially coincides with a height of an upper surface of thefirst insulating film; (j) removing the first insulating film andexposing a surface of the first conductive layer; (k) depositing asecond conductive layer on the first conductive layer and the secondinsulating film; (l) flattening the second conductive layer; and (m)patterning the second conductive layer and the first conductive layerand forming a gate electrode.

[0028] In a method of manufacturing a semiconductor device in thepresent invention, the step (l) is done by a CMP (Chemical MechanicalPolishing) method using the second insulating film as a stopper film.

[0029] In a method of manufacturing a semiconductor device in thepresent invention, it further includes the step of (n) of forming athird conductive layer on the second conductive layer after the step(l), and at the step (m), the second conductive layer, the firstconductive layer and the third conductive layer are patterned to therebyform a gate electrode and a gate pulling wiring pulled out from the gateelectrode.

[0030] In a method of manufacturing a semiconductor device in thepresent invention, the (b) or (h) is done such that an angle between aside and a bottom of the first conductive layer is obtuse.

[0031] In a method of manufacturing a semiconductor device in thepresent invention, the (b) or (h) is done such that an angle between aside and a bottom of the first conductive layer and an angle between aside and a bottom of the semiconductor layer are respectively obtuse.

[0032] In a method of manufacturing a semiconductor device in thepresent invention, the (b) or (h) is done such that an angle between aside and a bottom of the first conductive layer and an angle between aside and a bottom of the first insulating film are respectively obtuse.

[0033] In a method of manufacturing a semiconductor device in thepresent invention, the (b) or (h) is done such that an angle between aside and a bottom of the first conductive layer is a right angle.

[0034] In a method of manufacturing a semiconductor device in thepresent invention, the (b) or (h) includes the operation for performingthe RIE on the semiconductor layer, the gate insulating film, the firstconductive layer and the first insulating film.

[0035] In a method of manufacturing a semiconductor device in thepresent invention, the (b) or (h) is done by an etching operation forusing HBr—Cl₂—O₂—SF₆ system-gas.

[0036] In a method of manufacturing a semiconductor device in thepresent invention, the etching at the (b) or (h) is done by controllingthe inclinations of the respective sides of the semiconductor layer, thegate insulating film, the first conductive layer and the firstinsulating film since a flow rate of O₂ is adjusted.

[0037] In a method of manufacturing a semiconductor device in thepresent invention, the (c) or (i) includes the step of flattening thesecond insulating film by using the CMP method.

[0038] In a method of manufacturing a semiconductor device in thepresent invention, the first insulating film is a silicon nitride film,and the second insulating film is a silicon oxide film.

[0039] In a method of manufacturing a semiconductor device in thepresent invention, the first conductive layer or the second conductivelayer is made of poly-silicon.

[0040] A semiconductor device in the present invention is asemiconductor device in which a semiconductor layer is formed on aninsulating film, wherein the insulating film is not in contact with aconductive layer to form a gate electrode, and all of device isolationinsulating films formed on the insulating film are in contact with aninsulator.

[0041] A semiconductor device in the present invention is asemiconductor device in which a semiconductor layer is formed on aninsulating film, wherein the insulating film is not in contact with aconductive layer to form a gate electrode, and a device isolationinsulating film is not in contact with a conductive layer to form thegate electrode.

[0042] A semiconductor device in the present invention is asemiconductor device in which a semiconductor layer is formed on aninsulating film, wherein the insulating film is not in contact with aninsulating film to form a gate insulating film, and all of deviceisolation insulating films formed on the insulating film are in contactwith an insulator.

[0043] A semiconductor device in the present invention is asemiconductor device in which a semiconductor layer is formed on aninsulating film, wherein the insulating film is not in contact with aninsulating film to form a gate insulating film, and a device isolationinsulating film is not in contact with a conductive layer to form thegate electrode.

[0044] A semiconductor device in the present invention is asemiconductor device in which a semiconductor layer is formed on aninsulating film, wherein the semiconductor layer is not in contact withan insulating film to form a gate insulating film, and all of deviceisolation insulating films formed on the insulating film are in contactwith an insulator.

[0045] A semiconductor device in the present invention is asemiconductor device in which a semiconductor layer is formed on aninsulating film, wherein the semiconductor layer is not in contact withan insulating film to form a gate insulating film, and a deviceisolation insulating film is not in contact with a conductive layer toform the gate electrode.

[0046] In a semiconductor device in the present invention, an anglebetween a bottom of the semiconductor layer and a side in contact with adevice isolation insulating film of the semiconductor layer is obtuse.

[0047] In a semiconductor device in the present invention, a height ofan upper surface of the device isolation insulating film and a height ofan upper surface of a gate electrode are substantially equal to eachother.

[0048] In a semiconductor device in the present invention, the gateelectrode is provided with a first conductive material layer and asecond conductive material layer formed on an upper portion of the firstconductive material layer.

[0049] In a semiconductor device in the present invention, a height ofan upper surface of the gate electrode and a height of an upper surfaceof the device isolation insulating film are substantially equal to eachother.

[0050] In a semiconductor device in the present invention, thesemiconductor device is an SOI (Silicon On Insulator) device, and theinsulating film is a buried insulating film, and the semiconductor layeris a silicon film.

[0051] A semiconductor device in the present invention includes: asemiconductor layer having a source drain region and a channel regionpatterned in an island shape on an insulating film; a gate electrodeformed through a gate insulating film on an upper portion of thesemiconductor layer that is the channel region; and a device isolationinsulating film formed so as to surround the semiconductor layer on theinsulating film, in which its top surface is protruded upwardly from anupper surface of the semiconductor layer, wherein a side of the gateelectrode in contact with a side of the device isolation insulating filmis formed in a reverse tapered shape.

[0052] In a semiconductor device in the present invention, a side of thesemiconductor layer is formed in a reverse tapered shape.

[0053] In a semiconductor device in the present invention, a gateelectrode pulling wiring, which is in contact with an upper surface ofthe gate electrode and extended on an upper surface of the deviceisolation insulating film, is formed.

[0054] In a semiconductor device in the present invention, a firstconductive material layer constitutes the gate electrode and a secondconductive material layer formed thereon.

[0055] In a semiconductor device in the present invention, a height ofan upper surface of the device isolation insulating film and a height ofan upper surface of the gate electrode are substantially equal to eachother.

[0056] In a semiconductor device in the present invention, theinsulating film and the semiconductor layer are a buried insulating filmof an SOI substrate and a silicon film formed thereon.

BRIEF DESCRIPTION OF DRAWINGS

[0057]FIG. 1A is a step order sectional view showing a manufacturingmethod of a first conventional example in the present invention;

[0058]FIG. 1B is another step order sectional view showing amanufacturing method of a first conventional example in the presentinvention;

[0059]FIG. 1C is still another step order sectional view showing amanufacturing method of a first conventional example in the presentinvention;

[0060]FIG. 1D is still another step order sectional view showing amanufacturing method of a first conventional example in the presentinvention;

[0061]FIG. 2A is still another step order sectional view showing amanufacturing method of a first conventional example in the presentinvention;

[0062]FIG. 2B is still another step order sectional view showing amanufacturing method of a first conventional example in the presentinvention;

[0063]FIG. 2C is a plan view showing a manufacturing method of a firstconventional example in the present invention;

[0064]FIG. 3A is a step order sectional view showing a manufacturingmethod of a second conventional example in the present invention;

[0065]FIG. 3B is another step order sectional view showing amanufacturing method of a second conventional example in the presentinvention;

[0066]FIG. 3C is still another step order sectional view showing amanufacturing method of a second conventional example in the presentinvention;

[0067]FIG. 3D is still another step order sectional view showing amanufacturing method of a second conventional example in the presentinvention;

[0068]FIG. 4 is a sectional view describing a problem in theconventional examples;

[0069]FIG. 5A is a step order sectional view describing a problem in thefirst conventional example;

[0070]FIG. 5B is another step order sectional view describing a problemin the first conventional example;

[0071]FIG. 6A is a step order sectional view describing a problem in thesecond conventional example;

[0072]FIG. 6B is another step order sectional view describing a problemin the second conventional example;

[0073]FIG. 7A is a step order sectional view showing a manufacturingmethod in a first embodiment of the present invention;

[0074]FIG. 7B is another step order sectional view showing amanufacturing method in a first embodiment of the present invention;

[0075]FIG. 7C is still another step order sectional view showing amanufacturing method in a first embodiment of the present invention;

[0076]FIG. 7D is still another step order sectional view showing amanufacturing method in a first embodiment of the present invention;

[0077]FIG. 8A is still another step order sectional view showing amanufacturing method in a first embodiment of the present invention;

[0078]FIG. 8B is still another step order sectional view showing amanufacturing method in a first embodiment of the present invention;

[0079]FIG. 8C is still another step order sectional view showing amanufacturing method in a first embodiment of the present invention;

[0080]FIG. 8D is still another step order sectional view showing amanufacturing method in a first embodiment of the present invention;

[0081]FIG. 9 is a view showing a generation condition of a normal taperand a reverse taper in etching;

[0082]FIG. 10A is a sectional view showing a part of a generationprinciple of a normal taper and a reverse taper;

[0083]FIG. 10B is a sectional view showing another part of a generationprinciple of a normal taper and a reverse taper;

[0084]FIG. 11 is a comparison view between etching speeds of a siliconnitride film and a silicon oxide film in RIE;

[0085]FIG. 12A is a step order sectional view showing a manufacturingmethod in a second embodiment of the present invention;

[0086]FIG. 12B is another step order sectional view showing amanufacturing method in a second embodiment of the present invention;

[0087]FIG. 12C is still another step order sectional view showing amanufacturing method in a second embodiment of the present invention;

[0088]FIG. 12D is still another step order sectional view showing amanufacturing method in a second embodiment of the present invention;

[0089]FIG. 12E is still another step order sectional view showing amanufacturing method in a second embodiment of the present invention;

[0090]FIG. 13A is still another step order sectional view showing amanufacturing method in a second embodiment of the present invention;

[0091]FIG. 13B is still another step order sectional view showing amanufacturing method in a second embodiment of the present invention;

[0092]FIG. 13C is still another step order sectional view showing amanufacturing method in a second embodiment of the present invention;

[0093]FIG. 13D is still another step order sectional view showing amanufacturing method in a second embodiment of the present invention;

[0094]FIG. 14 is a comparison view between a polysilicon and a siliconoxide film;

[0095]FIG. 15A is a step order sectional view showing a manufacturingmethod in a third embodiment of the present invention;

[0096]FIG. 15B is another step order sectional view showing amanufacturing method in a third embodiment of the present invention;

[0097]FIG. 15C is still another step order sectional view showing amanufacturing method in a third embodiment of the present invention;

[0098]FIG. 15D is still another step order sectional view showing amanufacturing method in a third embodiment of the present invention;

[0099]FIG. 16A is still another step order sectional view showing amanufacturing method in a third embodiment of the present invention;

[0100]FIG. 16B is still another step order sectional view showing amanufacturing method in a third embodiment of the present invention;

[0101]FIG. 16C is still another step order sectional view showing amanufacturing method in a third embodiment of the present invention;

[0102]FIG. 16D is still another step order sectional view showing amanufacturing method in a third embodiment of the present invention;

[0103]FIG. 17A is a step order sectional view showing a manufacturingmethod in a fourth embodiment of the present invention;

[0104]FIG. 17B is another step order sectional view showing amanufacturing method in a fourth embodiment of the present invention;

[0105]FIG. 17C is still another step order sectional view showing amanufacturing method in a fourth embodiment of the present invention;

[0106]FIG. 17D is still another step order sectional view showing amanufacturing method in a fourth embodiment of the present invention;

[0107]FIG. 17E is still another step order sectional view showing amanufacturing method in a fourth embodiment of the present invention;

[0108]FIG. 18A is still another step order sectional view showing amanufacturing method in a fourth embodiment of the present invention;

[0109]FIG. 18B is still another step order sectional view showing amanufacturing method in a fourth embodiment of the present invention;

[0110]FIG. 18C is still another step order sectional view showing amanufacturing method in a fourth embodiment of the present invention;

[0111]FIG. 18D is still another step order sectional view showing amanufacturing method in a fourth embodiment of the present invention;

[0112]FIG. 19A is a step order sectional view showing a manufacturingmethod of a comparison example in the present invention;

[0113]FIG. 19B is another step order sectional view showing amanufacturing method of a comparison example in the present invention;

[0114]FIG. 19C is still another step order sectional view showing amanufacturing method of a comparison example in the present invention;

[0115]FIG. 20A is still another step order sectional view showing amanufacturing method of a comparison example in the present invention;

[0116]FIG. 20B is still another step order sectional view showing amanufacturing method of a comparison example in the present invention;and

[0117]FIG. 20C is still another step order sectional view showing amanufacturing method of a comparison example in the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0118] Embodiments of the present invention will be described below withreference to the drawings.

[0119] (First Embodiment)

[0120]FIGS. 7A to 7C are sectional views showing a manufacturing methodin a first embodiment of the present invention.

[0121] At first, as shown in FIG. 7A, an SOI substrate composed of asilicon substrate 11, a buried oxide film 12 and a silicon film 13 isprepared. Here, the film thickness of the silicon film 13 is as verythin as 10 nm. A gate insulating film 14, a first polysilicon film 15and a stopper nitride film 16 are deposited on this silicon film 13 inthis order (FIG. 7B).

[0122] Next, the stopper nitride film 16, the first polysilicon film 15,the gate insulating film 14 and the silicon film 13 are etched to formdevice isolation trenches in such a way that an etching end plane isvertical in the stopper nitride film 16 and has a reverse tapered planein the first polysilicon film 15, the gate insulating film 14 and thesilicon film 13 (i.e., an angle between a bottom plane and a side planeof the silicon film 13 is obtuse). Subsequently, an STI embeddedinsulating film 17 is deposited, and the STI embedded insulating film 17is flattened by a CMP method (FIG. 7C). In this case, the stoppernitride film 16, which is formed on the first polysilicon film 15,functions as a stopper in a CMP step. Thus, the first polysilicon film15 used to form the gate electrode is never damaged in the CMP step.

[0123] Here, a method of forming the etching end plane in a reversetapered shape or a forward tapered shape at the etching step will bedescribed. FIG. 9 shows a relation between a tapered angle (è) and aflow rate ratio of SF₆ gas in the etching in HBr—Cl₂—O₂—SF₆ system mixedgas atmosphere. As shown in FIG. 9, in case of usage of this mixed gas,the forward tapered shape is obtained as the flow rate ratio of the SF₆gas is increased, and the reverse tapered shape is obtained as the flowrate ratio of the SF₆ gas is decreased.

[0124] This reason could be considered as follows. FIGS. 10A and 10B areschematic sectional views showing the taper shape of a silicon layerwhen the silicon layer is etched in the HBr—Cl₂—O₂—SF₆ system mixed gasatmosphere, similarly to FIG. 9. FIG. 10A shows the shape of the formedtaper when the flow rate ratio of the SF₆ gas is low in this mixed gasatmosphere, and FIG. 10B shows the shape of the formed taper when theflow rate ratio of the SF₆ gas is high.

[0125] If the flow rate ratio of the SF₆ gas is low (FIG. 10A), in aninitial period of the etching operation, etching products are depositedto form a side protection film on a pattern end. This side protectionfilm has a function to protect the silicon layer from the etching, andit is difficult to carry out side etching near a boundary between a maskmaterial and the silicon layer. However, the side protection film is notformed in a lower region. Thus, the protection function against theetching by the side protection film becomes weak in the lower regionportion, and the side etching is carried out in the lower region portionof the silicon layer. Thus, the reverse tapered shape is obtained as thefinal shape (FIG. 10A).

[0126] On the contrary, as shown in FIG. 10B, if the flow rate ratio ofthe SF₆ gas is high, the side protection film is difficult to be formedduring the etching operation. Thus, there is no protection functionagainst the etching by the side protection film, and the side etching iscarried out from the initial period of the etching operation, and thelower region portion of the mask material is etched increasingly.Therefore, as the final shape, the forward tapered shape is obtained, inwhich the upper region portion of the silicon layer in the lower regionof the mask material is strongly affected by the side etching.

[0127] It should be noted that the comparison with the case when thedevice isolation trenches are formed to have the forward tapered shapewill be described later in [Comparison Example].

[0128] By the way, in this embodiment, both of the first polysiliconfilm 15 for the gate electrode and the silicon film 13 are reversetapered in the etching for forming the device isolation trenches.However, even if only the first polysilicon film 15 is reverse tapered,the residual polysilicon film can be protected when the gate electrodeportion is formed. This is because the silicon film 13 is not etchedwhen the gate electrode portion is formed.

[0129] Also, here, the stopper nitride film 16 is vertically etched.However, even if the stopper nitride film 16 is formed to have thereverse tapered shape, there is no problem.

[0130] Next, as shown in FIG. 7D, the stopper nitride film 16 and a partof the STI embedded insulating film 17 are removed to expose the firstpolysilicon film 15. At this time, in order to make the heights of thesurfaces of the first polysilicon film 15 and the STI embeddedinsulating film 17 equal to each other, the stopper nitride film 16 andthe STI embedded insulating film 17 are etched by the RIE of the samerate condition. Consequently, as shown in FIG. 7D, when the stoppernitride film 16 is removed, the heights of the first polysilicon film 15and the STI embedded insulating film 17 are made equal to each other.

[0131] The condition setting method of the same rate etching method willbe described below. FIG. 11 shows a relation between a flow rate ratioof O₂ gas and an etching rate of SiO₂ (the STI embedded insulating film17) and Si₃N₄ (the stopper nitride film 16). This data is obtained fromthe etching that uses the mixed gas of CHF₃—O₂—Ar system. From FIG. 11,it could be understood that in association with the increase in the flowrate ratio of the O₂ gas, the etching rate of the SiO₂ is made slower,and on the other hand, the etching rate of the Si₃N₄ is made faster, andboth of the etching rates become equal to each other at a certain point.

[0132] It should be noted that the etching operation to attain the stateshown in FIG. 7D is desired to be carried out under the same etchingrate condition. However, even if the etching can not be carried outunder the perfectly same condition, if a difference between both of theetching rates is within 20%, there is no special problem on an actualusage.

[0133] By the way, in the steps from FIG. 7C to FIG. 7D, if the stoppernitride film 16 is removed by using hot phosphoric acid, the STIembedded insulating film 17 protrudes upwardly by the thickness of thestopper nitride film 16 to generate a step. Such a step deteriorates theshape of the gate electrode at a next step of forming a gate electrode.However, this embodiment uses the same etching rate method to preventthe step from being generated between the first polysilicon film 15 andthe STI embedded insulating film 17. Thus, it is possible to attain thepatterning at a high accuracy.

[0134] Here, as the method of removing the step, the following method iseffective besides the same etching rate method. In FIG. 7C, the upperends of the stopper nitride film 16 and the STI embedded insulating film17 are flattened by the CMP method. Subsequently, the STI embeddedinsulating film 17 is etched up to the height of the lower portion ofthe stopper nitride film 16 by the RIE method in which its rate isfaster than that of the stopper nitride film 16 (FIG. 8D). Then, thestopper nitride film 16 is selectively removed by using the hotphosphoric acid.

[0135] Next, a second polysilicon film 18 is deposited for forming agate wiring line to connect the gate electrodes (FIG. 8A). Subsequently,a lithography and a high density plasma etching technique are used topattern the second and first polysilicon films to produce the laminationstructure of the gate electrode and the gate wiring line composed of thefirst polysilicon film 15 and the second polysilicon film 18 (FIG. 8B).

[0136] Next, a chemical vapor deposition (hereafter, referred to as CVD)method is used to form as an oxide film on the entire surface to havethe thickness of 80 nm. Subsequently, an anisotropic dry etching iscarried out to form side wall insulating films 20 on side walls of thegate electrode. Then, an ion implantation and a heat treatment are usedto form source and drain regions 21. Subsequently, a sputtering methodis used to deposit a cobalt film on the entire surface and then a heattreatment is carried out to form a silicide film 22. Then, anon-silicided cobalt film is removed. After an interlayer insulatingfilm 23 is formed thickly, contact holes are opened. The sputteringmethod is used to deposit a metal film of aluminum and the like, and themetal film is patterned to form a metal wiring 24 (FIG. 8C).

[0137] Here, the patterning for forming the gate electrode is carriedout to the structure in which the second polysilicon film 18 is flat(FIG. 8A). Also, the device isolation trench has the reverse taperedshape. Therefore, the polysilicon film is never left on the side wall ofthe STI embedded insulating film 17. Moreover, the electrical shortcircuit is never generated between the gate electrode and the source anddrain regions 21. Also, since the STI embedded insulating film 17 has aprotruding structure as compared with the silicon film 13, the sides ofthe silicon film are never covered with the gate electrode. Therefore,it is possible to suppress the reverse narrow channel effect that wasthe problem when the STI separation of the conventional method is used.Moreover, after the STI embedded insulating film 17 is embedded, it isnot necessary to carry out the HF process in order to remove the padoxide film (54 of FIG. 1C). Thus, unlike the case of the firstconventional example, the STI embedded insulating film 17 is neverreduced or lost. Thus, the over-etching of the buried oxide film 12under the end of the silicon film never occurs, the over-etching was theproblem conventionally in case of the usage of the very thin film SOIsubstrate. Therefore, the residual polysilicon film (a symbol 62 ofFIGS. 2A, B) is never generated. Also, the electric short circuit isnever generated between the gate electrodes and between the gateelectrode and the source drain region.

[0138] (Second Embodiment)

[0139]FIGS. 12A to 13D are sectional views showing a manufacturingmethod in a second embodiment of the present invention. At first, a gateinsulating film 14, a first polysilicon film 15 and a stopper nitridefilm 16 are deposited (FIG. 12B) in this order on an SOI substratecomposed of a silicon substrate 11, a buried oxide film 12 and a siliconfilm 13 having the film thickness of 10 nm, as shown in FIG. 12A.

[0140] Next, a stopper nitride film 16, a first polysilicon film 15, agate insulating film 14 and a silicon film 13 are selectively etched toform device isolation trenches. At this time, the sides of the stoppernitride film 16, the first polysilicon film 15 and the silicon film 13are etched to have the reverse tapered shapes. Subsequently, an STIembedded insulating film 17 is deposited, and the STI embeddedinsulating film 17 is flattened by the CMP method (FIG. 12C).

[0141] Next, the hot phosphoric acid is used to remove the stoppernitride film 16 to expose the surface of the first polysilicon film 15(FIG. 12D). Subsequently, the second polysilicon film 18 is deposited(FIG. 12E). Moreover, the CMP method is used to flatten the secondpolysilicon film 18 (FIG. 13A). At this CMP step, the STI embeddedinsulating film 17 can be used as a stopper film.

[0142] Here, FIG. 14 shows the change in the polishing amount of thepolysilicon film and the silicon oxide film (the STI embedded insulatingfilm) at the CMP step. From FIG. 14, it could be understood that thepolishing rate (the polishing amount per 1 min) of the polysilicon filmis about 1.5 times the polishing rate of the silicon oxide film, andwhen the polysilicon film is polished by the CMP method, the STIembedded insulating film can be used as the stopper.

[0143] Next, a third polysilicon film 25 is deposited to form a gatewiring line (FIG. 13B), and the lithography and the high density plasmaetching technique are used to pattern a laminated polysilicon film andto form the gate wiring line of the third polysilicon film 25, and thegate electrode of the lamination structure of the first polysilicon film15 and the first polysilicon film 18 (FIG. 13C). Subsequently, themethod similar to the method described in the first embodiment is usedto form side wall insulating films 20, source and drain regions 21 and asilicide film 22. An interlayer insulating film 23 is deposited, and ametal wiring 24 is formed to complete the MISFET (FIG. 13D).

[0144] In this embodiment, the same etching rate method is not used.While the state of the step is kept, a next step is carried out (FIG.12D). However, after the deposition of the second polysilicon film 18,since the STI embedded insulating film 17 functions as the stopper at atime of a next CMP step, the step between the second polysilicon film 18and the STI embedded insulating film 17 is removed (FIG. 13A). Moreover,after the third polysilicon film 25 is formed on the flat structure(FIG. 13B), the patterning is carried out to form the gate electrode.Thus, the generation of the residual polysilicon is suppressed.Therefore, it is possible to attain the effect similar to the firstembodiment. That is, the electric short circuit is never generatedbetween the gate electrode and the source and drain regions and betweenthe gate electrodes. Also, the reverse narrow channel effect issuppressed, which was the problem when the STI separation is used in theconventional method. Also, since the HF process is not carried out, theSTI embedded insulating film 17 is never reduced or lost.

[0145] (Third Embodiment)

[0146]FIGS. 15A to 16C are sectional views showing a manufacturingmethod in a third embodiment of the present invention. This embodimentis the method that does not give the reverse tapered shape to the firstpolysilicon film 15 and the silicon film 13.

[0147] As shown in FIG. 15A, a gate insulating film 14, a firstpolysilicon film 15 and a stopper nitride film 16 are deposited in thisorder on an SOI substrate having a silicon substrate 11, a buried oxidefilm 12 and a silicon film 13 (FIG. 15B). Subsequently, the stoppernitride film 16, the first polysilicon film 15, the gate insulating film14 and the silicon film 13 are selectively etched to form deviceisolation trenches such that the side plane of the device isolationtrench is vertical. Then, an STI embedded insulating film 17 isdeposited, and is flattened by the CMP method (FIG. 15C).

[0148] Next, when the stopper nitride film 16 is removed by using thesame etching rate method, a top surface of the first polysilicon film 15and a top surface of the STI embedded insulating film 17 are etched tobe substantially equal in height to each other (FIG. 15D). Also, insteadof this method, the STI embedded insulating film 17 may be first etchedto the stopper nitride film 16 (FIG. 16D), and then the stopper nitridefilm 16 may be removed through the hot phosphoric acid. Hereafter, theprocess is advanced in accordance with the method similar to the firstembodiment (FIGS. 16A, 16B), and the MISFET is completed (FIG. 16C).

[0149] In this method, the residual property of the polysilicon film atthe time of the formation of the gate electrode may be considered to bewrong as compared with the first embodiment, because a taper angle èwith the first polysilicon film 15 has the shape of a right angle.However, this embodiment suppresses the occurrence of the residualpolysilicon by flattening the first polysilicon film 15 and the STIembedded insulating film 17 by using the same etching rate method, or byetching the STI embedded insulating film 17 up to the lower end of thestopper nitride film 16 and removing it (FIG. 16D) and then removing thestopper nitride film 16 and flattening.

[0150] (Fourth Embodiment)

[0151]FIGS. 17A to 18D are sectional views showing a manufacturingmethod in a fourth embodiment of the present invention. As shown in FIG.17A, a gate insulating film 14, a first polysilicon film 15 and astopper nitride film 16 are deposited in this order on an SOI substratehaving a silicon substrate 11, a buried oxide film 12 and a silicon film13 (FIG. 17B). Subsequently, the stopper nitride film 16, the firstpolysilicon film 15, the gate insulating film 14 and the silicon film 13are selectively etched to form device isolation trenches whose sides arevertical. Then, an STI embedded insulating film 17 is deposited, and isflattened by the CMP method (FIG. 17C).

[0152] Next, the hot phosphoric acid is used to remove the stoppernitride film 16 to expose the surface of the first polysilicon film 15(FIG. 17D).

[0153] Next, a second polysilicon film 18 is deposited (FIG. 17E), andthe CMP method is used to flatten the second polysilicon film 18 (FIG.18A). In this CMP step, the STI embedded insulating film 17 can be usedas a stopper film.

[0154] Next, a third polysilicon film 25 for a gate wiring line isdeposited (FIG. 18B), and the lithography and the high density plasmaetching technique are used to pattern a laminated polysilicon film.Thus, the gate wiring line of the third polysilicon film 25, and thegate electrode of the lamination structure of the first polysilicon film15 and the second polysilicon film 18 are formed (FIG. 18C). After that,the method similar to the method noted in the first embodiment is usedto form side wall insulating films 20, source and drain regions 21 and asilicide film 22. An interlayer insulating film 23 is deposited, contactholes are opened, a metal wiring 24 is formed, and the MISFET iscompleted (FIG. 13D).

[0155] In this method, after the deposition of the second polysiliconfilm 18, the STI embedded insulating film 17 is used as the stopper, andthe CMP is carried out, and the flattening operation is carried out.Thus, it is possible to attain the effect similar to that described inthe second embodiment.

[0156] An actual example will be described below.

[0157] The example based on the first embodiment of the presentinvention will be described below with reference to FIGS. 7A to 7D and8A to 8D. At first, the SOI substrate is prepared which is composed ofthe silicon substrate 11, the buried oxide film 12 having the filmthickness of 50 nm to 100 nm and the silicon film 13 having thethickness of 10 nm (FIG. 7A). Subsequently, after the gate insulatingfilm 14 is formed to have the thickness of 1.5 nm, the first polysiliconfilm 15 and the stopper nitride film 16 are sequentially deposited tohave the thickness of 50 nm and the thickness of 50 nm, respectively(FIG. 7B).

[0158] Next, after a photolithography is used to form a resist film,this is used as a mask, and the stopper nitride film 16 is etched suchthat the etched side is vertical. Subsequently, the first polysiliconfilm 15, the gate insulating film 14 and the silicon film 13 aresequentially etched so as to be reverse tapered to form the deviceisolation trenches.

[0159] Next, the STI embedded insulating film 17 is deposited which iscomposed of a high density plasma oxide film having the thickness of 300nm, and the CMP method is used to flatten the STI embedded insulatingfilm 17 (FIG. 7C). Here, in a CMP method using a high purity ofcolloidal silica slurry, the polishing rate of the high density plasmaoxide film is equal to or greater than five times of the polishing rateof the nitride film. Thus, in the CMP polishing of the STI embeddedinsulating film 17, the stopper nitride film 16 sufficiently functionsas the stopper film even if the film thickness is 50 nm.

[0160] Next, the stopper nitride film 16 and the STI embedded insulatingfilm 17 are etched by the RIE of the same etching rate condition toexpose the first polysilicon film 15.

[0161] Next, in order to form a gate wiring line, the second polysiliconfilm 18 is deposited to have the thickness of 100 nm (FIG. 8A).Subsequently, the lithography and the high density plasma etching areused to pattern the laminated polysilicon film. Thus, the laminationstructure of the gate wiring line is formed which is composed of thesecond polysilicon film 18 and the gate electrode composed of the firstpolysilicon film 15 (FIG. 8B).

[0162] Next, the CVD method is used to deposit the silicon oxide film onthe entire surface to have the thickness of 80 nm. Then, the anisotropicetching is carried out to form the side wall insulating films 20. Then,the ion implantation and the heat treatment are used to form the sourceand drain regions 21. At this time, as the formation condition of thesource and drain regions, a source/drain layer in an nMISFET region isformed, for example, by carrying out an ion implantation of As⁺ under acondition of Energy: 8 keV, Dose: 4×10¹⁵ ions/cm⁻², and a source/drainlayer in a pMISFET region is formed, for example, by carrying out an ionimplantation of B⁺ under a condition of Energy: 2 keV, Dose: 5×10¹⁵ions/cm⁻². Moreover, an activating process (heat process) is carried outfor 10 seconds at 1010° C.

[0163] Thereafter, the silicide film 22 of CoSi₂ is formed to have thethickness of 5 nm. Subsequently, the interlayer insulating film 23 isformed to have the thickness of 500 nm. After the contact holes areopened, the metal wiring 24 is formed. Consequently, the MISFET iscompleted (FIG. 8C).

SECOND EXAMPLE

[0164] Another example for a second implementation of the presentinvention will be described below with reference to step order sectionalviews of FIGS. 12, 13.

[0165] At first, as shown in FIG. 12A, an SOI substrate is preparedwhich is composed of a silicon substrate 11, a buried oxide film 12having the thickness of 50 nm to 100 nm and the silicon film 13 havingthe thickness of 10 nm. Subsequently, a gate insulating film 14 isformed to have the thickness of 1.5 nm, and a first polysilicon film 15and a stopper nitride film 16 are sequentially deposited to have thethickness of 50 nm and the thickness of 50 nm, respectively (FIG. 12B).

[0166] Next, the photolithography is used to form a resist film, and byusing this as a mask, the stopper nitride film 16, the first polysiliconfilm 15, the gate insulating film 14 and the silicon film 13 aresequentially etched to be reverse tapered to form the device isolationtrenches. Subsequently, an STI embedded insulating film 17 is depositedwhich is composed of a high density plasma oxide film having thethickness of 300 nm, and the CMP method is used to flatten the STIembedded insulating film 17 (FIG. 12C).

[0167] Next, the hot phosphoric acid is used to remove the stoppernitride film 16 to expose the first polysilicon film 15 (FIG. 12D).Subsequently, a second polysilicon film 18 is deposited to have thethickness of 100 nm (FIG. 12E). After that, the CMP method is used toflatten the second polysilicon film 18 (FIG. 13A). Here, the STIembedded insulating film 17 functions as the stopper when the secondpolysilicon film 18 is flattened.

[0168] Next, as shown in FIG. 13B, a third polysilicon film 25 isdeposited to have the thickness of 100 nm to form a gate wiring line.Subsequently, the lithography and the high density plasma etchingtechnique are used to pattern the laminated polysilicon film. Thus, thegate wiring line is formed which is composed of the third polysiliconfilm 25 and the gate electrode is formed which is composed of thelamination structure of the second polysilicon film 18 and the firstpolysilicon film 15 (FIG. 13C).

[0169] Next, the CVD method is used to deposit the silicon oxide film onthe entire surface to have the thickness of 80 nm. Then, the anisotropicetching is carried out to form side wall insulating films 20. Afterthat, the ion implantation and the heat treatment are used to formsource and drain regions 21. As the formation condition of the sourcedrain region at this time, the source/drain layer in an nMISFET regionis formed, for example, by carrying out the ion implantation of As⁺under the condition of Energy: 8 keV, Dose: 4×10¹⁵ ions/cm⁻², and thesource/drain layer in a pMISFET region is formed, for example, bycarrying out the ion implantation of B⁺ under the condition of Energy: 2keV, Dose: 5×10¹⁵ ions/cm⁻². Moreover, the activating process (heatprocess) is done for 10 seconds at 1010° C.

[0170] Next, a silicide film 22 of CoSi₂ is formed to have the thicknessof 5 nm. Subsequently, an interlayer insulating film 23 is formed tohave the thickness of 500 nm. After contact holes are opened, a metalwiring 24 is formed. Then, the MISFET is completed (FIG. 8C).

COMPARISON EXAMPLE

[0171] Here, with regard to the first embodiment, an example when theetched shapes of the first polysilicon film 15, the gate insulating film14 and the silicon film 13 are processed so as to be forward taperedwill be described as a comparison example with reference to FIGS. 19A to20C.

[0172] Similarly to the first embodiment, the SOI substrate is preparedwhich is composed of the silicon substrate 11, the buried oxide film 12and the silicon film 13 (FIG. 19A). The gate insulating film 14, thefirst polysilicon film 15 and the stopper nitride film 16 aresequentially deposited thereon (FIG. 19B).

[0173] Next, after the stopper nitride film 16 is patterned such thatits end plane is vertical, the polysilicon film 15, the gate insulatingfilm 14 and the silicon film 13 are patterned so as to be forwardtapered (e is obtuse) to form the device isolation trench. Subsequently,the STI embedded insulating film 17 is deposited, and is flattened bythe CMP method (FIG. 19C). Subsequently, for example, the same etchingrate method is used to flatten the first polysilicon film 15 and the STIembedded insulating film 17 and then the second polysilicon film 18 isdeposited (FIG. 20A). Subsequently, by using the plasma etching at thestep of patterning the laminated polysilicon film, the lower portion ofthe end plane of the first polysilicon film 15 whose upper portion iscovered with the STI embedded insulating film 17 is not etched becauseof the shielding effect of the STI embedded insulating film 17 so thatthe residual polysilicon 19 is generated (FIG. 20C). This results in thegeneration of a leak current between the gate electrodes parallel toeach other and the increase in the parasitic capacitance at the gateelectrode and the like, since this residual polysilicon 19 is connectedto the gate electrode.

[0174] As described in this comparison example, if the device isolationtrench is formed to be forward tapered, the residual polysilicon 19 isgenerated. Thus, this is not desirable. Also, in SOI-MISFET of a shortchannel, there may be a case of generation of a leak current since adrain electric field is concentrated at a lower corner of an end of anelement region. However, if the silicon film 13 is also formed to bereverse tapered and the lower corner of the end of the element region isformed to be obtuse, the electric field is not easily concentrated. Thatis, if the device isolation trench has the reverse tapered shape, thisis desirable since the generation of the leak current can be suppressed.

[0175] In the semiconductor device of the present invention, thepolysilicon film for the gate electrode adjacent to the device isolationtrench is formed to be reverse tapered. Thus, when the gate electrode isformed, it is possible to previously prevent the generation of theresidual polysilicon. Also, it is possible to suppress the generation ofthe leak current between the gate electrodes and the increase in theparasitic capacitance at the gate electrode. Also, the device isolationinsulating film is formed to cover the side of the silicon film and toprotrude from the silicon film. Therefore, it is possible to suppressthe increase in the leak current and to suppress the occurrence of thereverse narrow channel effect. Moreover, since the silicon film is alsoformed to be reverse tapered, it is possible to relax the concentrationof the electric field and thereby reduce the leak current.

[0176] Also, in the manufacturing method according to the presentinvention, the HF process is not carried out at any step. Thus, it ispossible to remove the residual polysilicon caused by the over-etchingof the embedded oxide film. It is possible to previously prevent theelectric short circuit between the gate electrode and the source anddrain regions, the generation of the leak current between the gateelectrodes and the increase in the parasitic capacitance at the gateelectrode and the like. Also, since the photolithography step of formingthe gate electrode is carried out on the flat surface, it is possible toprevent the generation of the residual polysilicon and also possible tocarry out the patterning at the high accuracy.

INDUSTRIAL APPLICABILITY

[0177] The MISFET formed on the SOI substrate is expected to be the ULSIdevice of the sub 100 nm generation, since as compared with theconventional MISFET formed on the bulk substrate, it has the lowjunction capacitance and the small substrate bias effect and theexcellent sub-threshold effect.

1-28 (Canceled)
 29. A method of manufacturing a semiconductor devicecomprising: (a) sequentially forming a gate insulating film, a firstconductive layer and a first insulating film on a semiconductor layerprovided on an insulating film; (b) selectively removing saidsemiconductor layer, said gate insulating film, said first conductivelayer and said first insulating film to form a device isolation trench;(c) forming a second insulating film in said device isolation trench,wherein a height of an upper surface of said second insulating film issubstantially coincident with that of an upper surface of said firstinsulating film; (d) removing a part of said second insulating film andsaid first insulating film such that a height of an upper surface of theexposed first conductive layer is substantially coincident with that ofthe top surface of the second insulating film; and (e) patterning saidfirst conductive layer to form a gate electrode.
 30. The method ofmanufacturing the semiconductor device according to claim 29, whereinsaid (d) removing is carried out by using RIE (Reactive Ion Etching).31. The method of manufacturing the semiconductor device according toclaim 29, wherein said (d) removing comprises: removing the part of saidsecond insulating film by RIE; and removing said first insulating filmby a wet etching.
 32. The method of manufacturing the semiconductordevice according to claim 29, further comprising: (f) forming a secondconductive layer on said first conductive layer after said (d) removing,wherein said (e) patterning comprises: patterning said first conductivelayer and said second conductive layer to form said gate electrode and agate wiring connected from said gate electrode.
 33. The method ofmanufacturing the semiconductor device according to claim 29, whereinsaid (b) selectively removing is carried out such that an angle betweena side plane and a bottom plane in said first conductive layer isobtuse.
 34. The method of manufacturing the semiconductor deviceaccording to claim 29, wherein said (b) selectively removing is carriedout such that an angle between a side plane and a bottom plane in saidfirst conductive layer and an angle between a side plane and a bottomplane in said semiconductor layer are both obtuse.
 35. The method ofmanufacturing the semiconductor device according to claim 29, whereinsaid (b) selectively removing is carried out such that an angle betweena side plane and a bottom plane in said first conductive layer and anangle between a side plane and a bottom plane in said first insulatingfilm are both obtuse.
 36. The method of manufacturing the semiconductordevice according to claim 29, wherein said (b) selectively removing iscarried out such that an angle between a side plane and a bottom planein said first conductive layer is a right angle.
 37. The method ofmanufacturing the semiconductor device according to claim 29, whereinsaid (b) selectively removing comprises: carrying out an RIE to saidsemiconductor layer, said gate insulating film, said first conductivelayer and said first insulating film.
 38. The method of manufacturingthe semiconductor device according to claim 29, wherein said (b)selective removing is carried out by an etching using HBr—Cl₂—O₂—SF₆system gas.
 39. The method of manufacturing the semiconductor deviceaccording to claim 38, wherein said etching in said (b) selectiveremoving is carried out by controlling the inclinations of respectivesides of said semiconductor layer, said gate insulating film, said firstconductive layer and said first insulating film while adjusting a flowrate of O₂.
 40. The method of manufacturing the semiconductor deviceaccording to claim 29, wherein said (c) forming comprises: flatteningsaid second insulating film by using a CMP method.
 41. The method ofmanufacturing the semiconductor device according to claim 29, whereinsaid first insulating film comprises a silicon nitride film, and saidsecond insulating film comprises a silicon oxide film.
 42. The method ofmanufacturing the semiconductor device according to claim 29, whereinsaid first conductive layer or said second conductive layer comprisespolysilicon.
 43. A method of manufacturing a semiconductor devicecomprising: (g) sequentially forming a gate insulating film, a firstconductive layer and a first insulating film on a semiconductor layerprovided on an insulating film; (h) selectively removing saidsemiconductor layer, said gate insulating film, said first conductivelayer and said first insulating film to form a device isolation trench;(i) forming a second insulating film in said device isolation trench,wherein a height of an upper surface of said second insulating filmsubstantially coincident with that of an upper surface of the firstinsulating film; (j) removing said first insulating film to expose asurface of said first conductive layer; (k) depositing a secondconductive layer on said first conductive layer and said secondinsulating film; (l) flattening said second conductive layer; and (m)patterning said second conductive layer and said first conductive layerto form a gate electrode.
 44. The method of manufacturing thesemiconductor device according to claim 43, wherein said (l) flatteningis carried out by a CMP (Chemical Mechanical Polishing) by using saidsecond insulating film as a stopper film.
 45. The method ofmanufacturing the semiconductor device according to claim 43, furthercomprising: (n) forming a third conductive layer on said secondconductive layer after said (l) patterning, wherein said (m) flatteningcomprises: patterning said second conductive layer, said firstconductive layer and said third conductive layer to form a gateelectrode and a gate wiring connected with said gate electrode.
 46. Themethod of manufacturing the semiconductor device according to claim 43,wherein said (h) selectively removing is carried out such that an anglebetween a side plane and a bottom plane in said first conductive layeris obtuse.
 47. The method of manufacturing the semiconductor deviceaccording to claim 43, wherein said (h) selectively removing is carriedout such that an angle between a side plane and a bottom plane in saidfirst conductive layer and an angle between a side plane and a bottomplane in said semiconductor layer are both obtuse.
 48. The method ofmanufacturing the semiconductor device according to claim 43, whereinsaid (h) selectively removing is carried out such that an angle betweena side plane and a bottom plane in said first conductive layer and anangle between a side plane and a bottom plane in said first insulatingfilm are both obtuse.
 49. The method of manufacturing the semiconductordevice according to claim 43, wherein said (h) selective removing iscarried out such that an angle between a side plane and a bottom planein said first conductive layer is a right angle.
 50. The method ofmanufacturing the semiconductor device according to claim 43, whereinsaid (h) selectively removing comprises: carrying out an RIE to saidsemiconductor layer, said gate insulating film, said first conductivelayer and said first insulating film.
 51. The method of manufacturingthe semiconductor device according to claim 43, wherein said (h)selectively removing is carried out by an etching using HBr—Cl₂—O₂—SF₆system gas.
 52. The method of manufacturing the semiconductor deviceaccording to claim 51, wherein said etching in said (h) selectivelyremoving is carried out by controlling the inclinations of respectivesides of said semiconductor layer, said gate insulating film, said firstconductive layer and said first insulating film while adjusting a flowrate of O₂.
 53. The method of manufacturing the semiconductor deviceaccording to claim 43, wherein said (i) forming comprises: flatteningsaid second insulating film by using a CMP method.
 54. The method ofmanufacturing the semiconductor device according to claim 43, whereinsaid first insulating film comprises a silicon nitride film, and saidsecond insulating film comprises a silicon oxide film.
 55. The method ofmanufacturing the semiconductor device according to claim 43, whereinsaid first conductive layer or said second conductive layer comprisespolysilicon.
 56. A semiconductor device in which a semiconductor layeris formed on an insulating film, wherein said insulating film is not incontact with a conductive layer for a gate electrode, and a whole ofdevice isolation insulating films formed on said insulating film are incontact with an insulator.
 57. A semiconductor device in which asemiconductor layer is formed on an insulating film, wherein saidinsulating film is not in contact with a conductive layer for a gateelectrode, and a device isolation insulating film is not in contact withsaid conductive layer for said gate electrode.
 58. A semiconductordevice in which a semiconductor layer is formed on an insulating film,wherein said insulating film is not in contact with an insulating filmfor a gate insulating film, and a whole of device isolation insulatingfilms formed on said insulating film are in contact with an insulator.59. A semiconductor device in which a semiconductor layer is formed onan insulating film, wherein said insulating film is not in contact withan insulating film for a gate insulating film, and a device isolationinsulating film is not in contact with said conductive layer for saidgate electrode.
 60. The semiconductor device according to claim 56,wherein an angle between a bottom plane of said semiconductor layer anda side of said semiconductor layer contacting said device isolationinsulating film is obtuse.
 61. The semiconductor device according toclaim 56, wherein a height of an upper surface of said device isolationinsulating film and that of an upper surface of said gate electrode aresubstantially equal to each other.
 62. The semiconductor deviceaccording to claim 56, wherein said gate electrode comprises: a firstconductive material layer; and a second conductive material layer formedon an upper portion of said first conductive material layer.
 63. Thesemiconductor device according to claim 56, wherein a height of an uppersurface of said gate electrode and that of an upper surface of saiddevice isolation insulating film are substantially equal to each other.64. The semiconductor device according to claim 56, wherein saidsemiconductor device comprises an SOI (Silicon On Insulator) device, andsaid insulating film comprises a buried insulating film, and saidsemiconductor layer comprises a silicon film.
 65. The semiconductordevice comprising: a semiconductor layer having a channel region andsource/drain regions which are formed by patterning in an island manneron an insulating film; a gate electrode formed on said channel region ofsaid semiconductor layer through a gate insulating film; and a deviceisolation insulating film formed on said insulating film to surroundsaid semiconductor layer and having an upper surface protruding from anupper surface of said semiconductor layer, wherein a side plane of saidgate electrode contacting a side plane of said device isolationinsulating film is formed to be reverse tapered.
 66. The semiconductordevice according to claim 65, wherein a side plane of said semiconductorlayer is formed to be reverse tapered.
 67. The semiconductor deviceaccording to claim 65, wherein a gate wiring line is formed on said gateelectrode.
 68. The semiconductor device according to claim 65, wherein agate wiring line is formed to contact an upper surface of said gateelectrode and to extend to said upper surface of said device isolationinsulating film.
 69. The semiconductor device according to claim 65,wherein said gate electrode comprises a first conductive material layerand a second conductive material layer on said first conductive materiallayer.
 70. The semiconductor device according to claim 65, wherein aheight of said upper surface of said device isolation insulating film issubstantially equal to that of an upper surface of said gate electrode.71. The semiconductor device according to claim 65, wherein saidinsulating film and said semiconductor layer are a buried insulatingfilm and a silicon film formed on the buried insulating film in a SOIsubstrate, respectively.